HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 422

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Serial Communication Interface (SCI)
14.3.6
The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock
output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCSCR.
Rev. 5.00 May 29, 2006 page 372 of 698
REJ09B0146-0500
Bit
7
6
Bit Name
TIEs
RIE
Serial Control Register (SCSCR)
Initial Value
0
0
R/W
R/W
R/W
Description
Transmit Interrupt Enable
Enables or disables the TXI request when the serial
transmit data is transferred from SCTDR to SCTCR and
the TDRE in SCSSR is set to 1.
0: Transmit-data-empty interrupt request (TXI) is
1: Transmit-data-empty interrupt request (TXI) is
Receive Interrupt Enable
Enables or disables the receive-data-full interrupt (RXI)
request when the serial receive data is transferred from
SCRSR to SCRDR and the receive data register full bit
(RDRF) in SCSSR is set to 1. It also enables or
disables receive-error interrupt (ERI) requests.
0: Receive-data-full interrupt (RXI) and receive-error
1: Receive-data-full interrupt (RXI) and receive-error
disabled
enabled
Note: The TXI interrupt request can be cleared by
reading TDRE after it has been set to 1, then
clearing TDRE to 0, or by clearing TIE to 0.
interrupt (ERI) requests are disabled
Note: RXI and ERI interrupt requests can be cleared
by reading 1 from the RDRF flag or error flag (FER,
PER, or ORER) then clearing the flag to 0, or by
clearing RIE to 0.
interrupt (ERI) requests are enabled