HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 27

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.5
Section 5 Cache
5.1
5.2
5.3
5.4
Section 6 Interrupt Controller (INTC)
6.1
6.2
6.3
6.4
6.5
4.4.2
4.4.3
Usage Note........................................................................................................................ 97
Feature .............................................................................................................................. 99
5.1.1
Register Description.......................................................................................................... 101
5.2.1
5.2.2
Operation .......................................................................................................................... 105
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Memory-Mapped Cache ................................................................................................... 108
5.4.1
5.4.2
5.4.3
Feature .............................................................................................................................. 113
Input/Output Pin................................................................................................................ 115
Interrupt Sources............................................................................................................... 115
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Register Description.......................................................................................................... 123
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Operation .......................................................................................................................... 133
6.5.1
6.5.2
General Exceptions .............................................................................................. 92
Interrupts.............................................................................................................. 95
Cache Structure.................................................................................................... 99
Cache Control Register (CCR) ............................................................................ 101
Cache Control Register 2 (CCR2)........................................................................ 102
Searching the Cache............................................................................................. 105
Read Access ......................................................................................................... 106
Prefetch Operation ............................................................................................... 107
Write Access ........................................................................................................ 107
Write-Back Buffer ............................................................................................... 107
Coherency of Cache and External Memory ......................................................... 108
Address Array ...................................................................................................... 108
Data Array............................................................................................................ 109
Usage Examples................................................................................................... 111
NMI Interrupts ..................................................................................................... 115
IRQ Interrupt........................................................................................................ 116
IRL Interrupts ...................................................................................................... 117
On-Chip Peripheral Module Interrupts ................................................................ 118
Interrupt Exception Processing and Priority ........................................................ 119
Interrupt Priority Registers A to E (IPRA to IPRE)............................................. 124
Interrupt Control Register 0 (ICR0)..................................................................... 125
Interrupt Control Register 1 (ICR1)..................................................................... 126
Interrupt Request Register 0 (IRR0) .................................................................... 129
Interrupt Request Register 1 (IRR1) .................................................................... 131
Interrupt Request Register 2 (IRR2) .................................................................... 132
Interrupt Sequence ............................................................................................... 133
Multiple Interrupts ............................................................................................... 135
.................................................................................................................... 99
........................................................................... 113
Rev. 5.00 May 29, 2006 page xxv of xlviii