HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 49

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 16.4
Table 16.5
Table 16.6
Table 16.7
Table 16.8
Table 16.9
Section 17 Pin Function Controller (PFC)
Table 17.1
Section 18 I/O Ports
Table 18.1
Table 18.2
Table 18.3
Table 18.4
Table 18.5
Table 18.6
Table 18.7
Table 18.8
Table 18.9
Table 18.10 Read/Write Operation of the SC Port Data Register (SCPDR) .............................. 527
Section 19 A/D Converter (ADC)
Table 19.1
Table 19.2
Table 19.3
Table 19.4
Table 19.5
Section 20 D/A Converter (DAC)
Table 20.1
Section 21 User Debugging Interface (H-UDI)
Table 21.1
Table 21.2
Table 21.3
Section 22 Power-Down Modes
Table 22.1
Table 22.2
Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)............................................................................................ 465
Maximum Bit Rates during External Clock Input (Asynchronous Mode) ............. 465
SCSMR2 Settings and SCIF Communication Formats .......................................... 469
SCSCR2 and SCSCR2 Settings and SCIF Clock Source Selection ....................... 470
Serial Communication Formats.............................................................................. 470
SCIF Interrupt Sources........................................................................................... 480
List of Multiplexed Pins ......................................................................................... 485
Read/Write Operation of the Port A Data Register (PADR) .................................. 508
Read/Write Operation of the Port C Data Register (PCDR) .................................. 512
Read/Write Operation of the Port E Data Register (PEDR)................................... 516
Read/Write Operation of the Port F Data Register (PFDR) ................................... 518
Read/Write Operation of the Port G Data Register (PGDR) .................................. 520
Read/Write Operation of the Port H Data Register (PHDR) .................................. 522
Read/Write Operation of the Port J Data Register (PJDR)..................................... 524
A/D Converter Pins ................................................................................................ 531
Analog Input Channels and A/D Data Registers .................................................... 532
A/D Conversion Time (Single Mode) .................................................................... 544
Analog Input Pin Ratings ....................................................................................... 547
Relationship between Access Size and Read Data ................................................. 548
D/A Converter Pins ................................................................................................ 550
Pin Configuraiton ................................................................................................... 554
This LSI's Pins and Boundary Scan Register Bits .................................................. 556
Reset Configuration................................................................................................ 562
Power-Down Modes............................................................................................... 568
Pin Configuration ................................................................................................... 569
Read/Write Operation of the Port B Data Register (PBDR) ................................. 510
Read/Write Operation of the Port D Data Register (PDDR) ................................. 514
Rev. 5.00 May 29, 2006 page xlvii of xlviii