HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 312

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 Direct Memory Access Controller (DMAC)
Notes: 1. Only 0 can be written to the TE bit after 1 is read.
Rev. 5.00 May 29, 2006 page 262 of 698
REJ09B0146-0500
Bit
1
0
2. DI, RO, RL, AM, AL, and DS bits are not included in some channels.
Bit Name
TE
DE
Initial Value
0
0
R/W
R/(W) *
R/W
1
Description
Transfer End
TE is set to 1 when data transfer ends by the
count specified in DMATCR. At this time, if the IE
bit is set to 1, an interrupt request is generated.
Before this bit is set to 1, if data transfer ends due
to an NMI interrupt, a DMAC address error, or
clearing the DE bit or the DME bit in DMAOR, this
bit is not set to 1. Even if the DE bit is set to 1
while this bit is set to 1, transfer is not enabled.
0: Data transfer does not end by the count
1: Data transfer ends by the specified count
DMAC Enable
DE enables channel operation.
0: Disables channel operation
1: Enables channel operation
Note: If an auto request is specifies (specified in
specified in DMATCR
Clear condition: Writing 0 after TE = 1 read at
power-on reset or manual reset
RS3 to RS0), transfer starts when this bit
is set to 1. In an external request or an
internal module request, transfer starts if
transfer request is generated after this bit
is set to 1. Clearing this bit during transfer
can terminate transfer.
Even if the DE bit is set, transfer is not
enabled if the TE bit is 1, the DME bit in
DMAOR is 0, or the NMIF bit in DMAOR is
1.