HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 137

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

If the SPC and SSR have been saved in the external memory, set the BL bit in SR to 1, then
restore the SPC and SSR, and issue an RTE instruction.
4.2
There are four registers related to exception processing. These are peripheral module registers, and
therefore reside in area P4. They can be accessed by specifying the address in the privileged mode
only.
There are following four registers related to exception processing. Registers with undefined initial
values (TRAPA exception register, Interrupt event register, and Interrupt event register 2) should
be initialized by software. Refer to section 23, List of Registers, for more details of the addresses
and access sizes.
4.2.1
The exception event register (EXPEVT) contains a 12-bit exception code. The exception code set
in EXPEVT is that for a reset or general exception event. The exception code is set automatically
by hardware when an exception occurs. EXPEVT can also be modified by software.
Note:
Bit
31 to 12
11 to 0
Exception event register (EXPEVT)
Interrupt event register (INTEVT)
Interrupt event register 2 (INTEVT2)
TRAPA exception register (TRA)
* H'0000 is set in a power-on reset, and H'020 in a manual reset.
Register Description
Exception Event Register (EXPEVT)
Bit Name
Initial Value R/W
All 0
*
R
R/W
Description
Reserved
These bits are always read as 0. The
write value should always be 0.
12-bit exception code
Rev. 5.00 May 29, 2006 page 87 of 698
Section 4 Exception Processing
REJ09B0146-0500