HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 220

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Bus State Controller (BSC)
Shadow Space: Areas 0, 2 to 6 are decoded by physical addresses A28 to A26, which correspond
to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0
addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the
address space obtained by adding to it H'20000000 n (n
which is on-chip I/O space, is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +
H'20000000
space is reserved, so do not use it.
8.3.1
This LSI supports PCMCIA standard interface specifications in physical space areas 5 and 6
(except for WP).
The interfaces supported are basically the "IC memory card interface" and "I/O card interface"
stipulated in JEIDA Specifications Ver. 4.2 (PCMCIA2.1).
Table 8.4
Note:
Rev. 5.00 May 29, 2006 page 170 of 698
REJ09B0146-0500
Item
Access
Data bus
Memory type
Memory capacity
I/O space capacity
Others
* Dynamic bus sizing of I/O bus width is supported only in the little endian mode.
PCMCIA Support
PCMCIA Interface Characteristics
n–H'1FFFFFFF + H'20000000 n (n
Area 6: H'1A000000
Area 5: H'14000000
Area 5: H'16000000
Area 6: H'18000000
Feature
Random access
8/16 bits
Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM
Maximum 32 Mbytes
Maximum 32 Mbytes
Dynamic bus sizing of I/O bus width *
The PCMCIA interface can be accessed from the address translation
area or non-address translation area.
Figure 8.4 PCMCIA Space Allocation
Commom memory/Attribute memory
Commom memory/Attribute memory
I/O space
I/O space
0 to 7) corresponding to the area 7 shadow
1 to 6). The address range for area 7,