HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 211

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Break Condition Specified to a CPU Data Access Cycle
1. Register specifications
Break Condition Specified to a DMAC Data Access Cycle
1. Register specifications:
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
•
On channel A, a user break occurs with ASID = H'80 during longword read to address
H'00123454, word read to address H'00123456, or byte read to address H'00123456. On
channel B, a user break occurs with ASID = H'70 when word H'A512 is written in addresses
H'000ABC00 to H'000ABCFE.
BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555,
BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00000078, BDMRB = H'0000000F,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
•
On channel A, no user break occurs since instruction fetch is not performed in DMAC cycles.
On channel B, a user break occurs with ASID = H'70 when the DMAC writes byte H'7* in
address H'00055555.
Address:
Bus cycle: CPU/data access/read (operand size is not included in the condition)
Address:
Data:
Bus cycle: CPU/data access/write/word
Address:
Bus cycle: DMAC/instruction fetch/read (operand size is not included in the condition)
Address:
Data:
Bus cycle: DMAC/data access/write/byte
Channel A
Channel B
Channel A
Channel B
H'00123456, Address mask: H'00000000
H'000ABCDE, Address mask: H'000000FF, ASID: H'70
H'0000A512, Data mask: H'00000000
H'00314156, Address mask: H'00000000, ASID: H'80
H'00055555, Address mask: H'00000000, ASID: H'70
H'00000078, Data mask: H'0000000F
Rev. 5.00 May 29, 2006 page 161 of 698
Section 7 User Break Controller
REJ09B0146-0500