HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 142

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Exception Processing
Table 4.3
4.4.2
Rev. 5.00 May 29, 2006 page 92 of 698
REJ09B0146-0500
Type
Power-on reset
Manual reset
H-UDI reset
TLB miss exception
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0400.
To speed up TLB miss processing, the offset differs from other exceptions.
TLB invalid exception
The PC and SR of the instruction that generated the exception are saved in the SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC
Conditions: Comparison of TLB addresses shows no address match
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The RC bit in MMUCR is
incremented by one when all ways are valid, or way-0 is set to the RC with top priority
when there is invalid way.
Conditions: Comparison of TLB addresses shows address match but V = 0.
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
General Exceptions
Types of Reset
Conditions for Transition
to Reset State
RESETP = Low
RESETM = Low
H-UDI reset command input
VBR + H'0100.
CPU
Initialized
Initialized
Initialized
On-Chip Supporting Modules
(See register configuration in
relevant sections)
Internal State