HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 202

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 7 User Break Controller
7.2.12
BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the
flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and
also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight
BRDR registers have queue structure and a stored register is shifted every branch.
7.2.13
Break ASID register A (BASRA) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel A. It is not initialized by resets. It is located in CCN.
Rev. 5.00 May 29, 2006 page 152 of 698
REJ09B0146-0500
Bit
31
30 to 28
27 to 0
Bit
7 to 0
Branch Destination Register (BRDR)
Break ASID Register A (BASRA)
Bit Name
DVF
—
BDA27 to
BDA0
Bit Name
BASA7 to
BASA0
Initial Value
0
—
—
Initial Value
—
R/W
R
R
R
R/W
R/W
Description
BRDR Valid Flag
Indicates whether a branch destination address is
stored. When a branch destination address is
fetched, this flag is set to 1. This flag is set to 0 in
reading BRDR.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
Reserved
These bits are always read as 0. The write value
should always be 0.
Branch Destination Address
These bits store the first fetched address after
branch.
Description
Break ASID
These bits store the ASID (bits 7 to 0) that is the
channel A break condition.