HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 74

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 CPU
Addressing
Mode
Register
indirect with
displacement
Indexed
register
indirect
GBR indirect
with
displacement
Indexed
GBR
indirect
Rev. 5.00 May 29, 2006 page 24 of 698
REJ09B0146-0500
Instruction
Format
@(disp:4,
Rn)
@(R0, Rn) Effective address is sum of register Rn and
@(disp:8,
GBR)
@(R0,
GBR)
Effective Address Calculation Method
Effective address is register Rn contents
with 4-bit displacement disp added.
After disp is zero-extended, it is multiplied
by 1 (byte), 2 (word), or 4 (longword),
according to the operand size.
R0 contents.
Effective address is register GBR contents
with 8-bit displacement disp added.
After disp is zero-extended, it is multiplied
by 1 (byte), 2 (word), or 4 (longword),
according to the operand size.
Effective address is sum of register GBR
and R0 contents.
(zero-extended)
(zero-extended)
GBR
1/2/4
disp
GBR
1/2/4
Rn
R0
disp
R0
Rn
+
+
+
+
+ disp
+ disp
GBR + R0
Rn + R0
GBR
Rn
1/2/4
1/2/4
Calculation Formula
Byte: Rn + disp
Word: Rn + disp × 2
Longword: Rn + disp ×
4
Rn + R0
Byte: GBR + disp
Word: GBR + disp × 2
Longword: GBR + disp
× 4
GBR + R0