HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 248

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Bus State Controller (BSC)
Table 8.11 32-Bit External Device/Big Endian Access and Data Alignment
Operation
Byte access at 0
Byte access at 1
Byte access at 2
Byte access at 3
Word access at 0
Word access at 2
Longword access
at 0
Table 8.12 16-Bit External Device/Big Endian Access and Data Alignment
Operation
Byte access at 0
Byte access at 1
Byte access at 2
Byte access at 3
Word access at 0
Word access at 2
Longword
access
at 0
Rev. 5.00 May 29, 2006 page 198 of 698
REJ09B0146-0500
1st
time at 0
2nd
time at 2
D31 to
D24
Data
7 to 0
—
—
—
Data
15 to 8
—
Data
31 to 24
D31 to
D24
—
—
—
—
—
—
—
—
D23 to
D16
—
—
—
—
—
—
—
—
D23 to
D16
—
Data
7 to 0
—
—
Data
7 to 0
—
Data
23 to 16
Data Bus
Data Bus
D15 to
D8
Data
7 to 0
—
Data
7 to 0
—
Data
15 to 8
Data
15 to 8
Data
31 to 24
Data
15 to 8
D15 to
D8
—
—
Data
7 to 0
—
—
Data
15 to 8
Data
15 to 8
Data
Data
D7 to
D0
—
7 to 0
—
7 to 0
Data
7 to 0
Data
7 to 0
Data
23 to 16
Data
7 to 0
D7 to
D0
—
—
—
Data
7 to 0
—
Data
7 to 0
Data
7 to 0
WE3
WE3,
DQMUU
DQMUU
WE3
WE3
DQMUU
DQMUU
WE3
WE3,
WE3
WE3
DQMUU
DQMUU
DQMUU
DQMUU
Assert
Assert
Assert
WE2
WE2,
DQMUL
DQMUL
WE2
WE2
DQMUL
DQMUL
WE2
WE2,
WE2
WE2
DQMUL
DQMUL
DQMUL
DQMUL
Assert
Assert
Assert
Strobe Signals
Strobe Signals
WE1
WE1
WE1
WE1,
DQMLU
DQMLU
DQMLU
DQMLU
Assert
Assert
Assert
Assert
Assert
Assert
WE1
WE1,
WE1
WE1
DQMLU
DQMLU
DQMLU
DQMLU
Assert
Assert
Assert
WE0
WE0
WE0
WE0,
DQMLL
DQMLL
DQMLL
DQMLL
Assert
Assert
Assert
Assert
Assert
Assert
WE0
WE0,
WE0
WE0
DQMLL
DQMLL
DQMLL
DQMLL
Assert
Assert
Assert