HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 26

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.4
3.5
3.6
3.7
Section 4 Exception Processing
4.1
4.2
4.3
4.4
Rev. 5.00 May 29, 2006 page xxiv of xlviii
3.3.3
3.3.4
MMU Functions................................................................................................................ 66
3.4.1
3.4.2
3.4.3
3.4.4
MMU Exceptions.............................................................................................................. 70
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
Configuration of the Memory-Mapped TLB .................................................................... 77
3.6.1
3.6.2
3.6.3
Usage Note........................................................................................................................ 79
3.7.1
3.7.2
Exception Processing Function ......................................................................................... 81
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
Register Description.......................................................................................................... 87
4.2.1
4.2.2
4.2.3
4.2.4
Operation .......................................................................................................................... 89
4.3.1
4.3.2
4.3.3
Individual Exception Operations....................................................................................... 91
4.4.1
TLB Address Comparison ................................................................................... 63
Page Management Information............................................................................ 65
MMU Hardware Management ............................................................................. 66
MMU Software Management .............................................................................. 66
MMU Instruction (LDTLB)................................................................................. 67
Avoiding Synonym Problems .............................................................................. 68
TLB Miss Exception ............................................................................................ 70
TLB Protection Violation Exception ................................................................... 71
TLB Invalid Exception ........................................................................................ 72
Initial Page Write Exception ................................................................................ 73
Processing Flow in Event of MMU Exception
(Same Processing Flow for CPU Address Error)................................................. 75
Address Array ...................................................................................................... 77
Data Array............................................................................................................ 77
Usage Examples................................................................................................... 79
Use of Instructions Manipulating MD and BL Bits in SR ................................... 79
Use of TLB .......................................................................................................... 80
Exception Processing Flow.................................................................................. 81
Exception Processing Vector Addresses.............................................................. 82
Acceptance of Exceptions.................................................................................... 83
Exception Codes .................................................................................................. 85
Exception Request and BL Bit............................................................................. 86
Returning from Exception Processing ................................................................. 86
Exception Event Register (EXPEVT).................................................................. 87
Interrupt Event Register (INTEVT) ..................................................................... 88
Interrupt Event Register 2 (INTEVT2) ................................................................ 88
TRAPA Exception Register (TRA) ..................................................................... 89
Reset..................................................................................................................... 89
Interrupts.............................................................................................................. 90
General Exceptions .............................................................................................. 90
Resets ................................................................................................................... 91
....................................................................................... 81