HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 28

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

6.6
Section 7 User Break Controller
7.1
7.2
7.3
7.4
Section 8 Bus State Controller (BSC)
8.1
8.2
8.3
8.4
Rev. 5.00 May 29, 2006 page xxvi of xlviii
Interrupt Response Time................................................................................................... 135
Feature .............................................................................................................................. 139
Register Description.......................................................................................................... 141
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10 Execution Times Break Register (BETR)............................................................ 150
7.2.11 Branch Source Register (BRSR).......................................................................... 151
7.2.12 Branch Destination Register (BRDR) .................................................................. 152
7.2.13 Break ASID Register A (BASRA)....................................................................... 152
7.2.14 Break ASID Register B (BASRB) ....................................................................... 153
Operation .......................................................................................................................... 153
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Usage Note........................................................................................................................ 162
Feature .............................................................................................................................. 163
Input/Output Pin................................................................................................................ 165
Area Overview .................................................................................................................. 166
8.3.1
Register Description.......................................................................................................... 173
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
Break Address Register A (BARA) ..................................................................... 141
Break Address Mask Register A (BAMRA)........................................................ 142
Break Bus Cycle Register A (BBRA) .................................................................. 142
Break Address Register B (BARB)...................................................................... 144
Break Address Mask Register B (BAMRB) ........................................................ 144
Break Data Register B (BDRB) ........................................................................... 144
Break Data Mask Register B (BDMRB).............................................................. 145
Break Bus Cycle Register B (BBRB) .................................................................. 145
Break Control Register (BRCR) .......................................................................... 147
Flow of the User Break Operation ....................................................................... 153
Break on Instruction Fetch Cycle......................................................................... 154
Break by Data Access Cycle................................................................................ 154
Sequential Break .................................................................................................. 155
Value of Saved Program Counter ........................................................................ 155
PC Trace .............................................................................................................. 156
Usage Examples................................................................................................... 158
PCMCIA Support ................................................................................................ 170
Bus Control Register 1 (BCR1) ........................................................................... 174
Bus Control Register 2 (BCR2) ........................................................................... 177
Wait State Control Register 1 (WCR1)................................................................ 179
Wait State Control Register 2 (WCR2)................................................................ 182
Individual Memory Control Register (MCR)....................................................... 186
PCMCIA Control Register (PCR)........................................................................ 190
..................................................................................... 139
........................................................................... 163