HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 618

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 22 Power-Down Modes
Table 22.1 Power-Down Modes
Mode
Sleep
mode
Software
standby
mode
Module
standby
function
Hardware
standby
mode
Notes: 1. The RTC still runs if the START bit in RCR2 is set to 1 (see section 13, Realtime Clock
Rev. 5.00 May 29, 2006 page 568 of 698
REJ09B0146-0500
2. Depends on the on-chip supporting module.
3. The RTC still runs if the START bit in RCR2 is set to 1. TMU does not run.
4. When the LSI enters sleep mode, the CPU halts.
5. If the realtime clock (RTC) is set to module standby mode (bit 1 in standby control
Transition
Conditions
Execute SLEEP
instruction with
STBY bit cleared
to 0 in STBCR
Execute SLEEP
instruction with
STBY bit set to 1
in STBCR
Set MSTP bit of
STBCR to 1 *
Drive CA pin low
(RTC)). TMU still runs when output of the RTC is used as input to its counter (see
section 12, Timer Unit (TMU)).
TMU external pin: Held
SCI external pin: Reset
register (STBCR) set to 1) before any register in the RTC, SCI, or TMU is accessed,
registers in the serial communication interface (SCI) or timer unit (TMU) may not be
read properly. To avoid this problem, access (read or write) any register in the RTC,
SCI, or TMU once or more before setting the RTC to module standby mode.
5
CPG
Runs Halts Held
Halts Halts Held
Runs Runs
Halts Halts Held
CPU
*
4
CPU
Reg-
ister
Held
On-Chip
Memory
Held
Held
Held
Held
State
On-Chip
Peripheral
Modules
Runs
Halts *
Specified
module
halts
Halts *
1
3
Pins
Held
Held
*
Held
2
External
Memory
Refresh
Self-
refresh
Refresh
Self-
refresh
Canceling
Procedure
1. Interrupt
2. Reset
1. Interrupt
2. Reset
1. Clear MSTP
2. Power-on
Power-on reset
bit to 0
reset