HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 34

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

18.6 Port F................................................................................................................................. 517
18.7 Port G................................................................................................................................ 519
18.8 Port H................................................................................................................................ 521
18.9 Port J ................................................................................................................................. 523
18.10 SC Port .............................................................................................................................. 525
Section 19 A/D Converter (ADC)
19.1 Features ............................................................................................................................. 529
19.2 Input/Output Pin................................................................................................................ 531
19.3 Register Description.......................................................................................................... 531
19.4 Bus Master Interface ......................................................................................................... 536
19.5 Access Size of A/D Data Register..................................................................................... 538
19.6 Operation .......................................................................................................................... 539
19.7 Interrupt Requests ............................................................................................................. 545
19.8 Definitions of A/D Conversion Accuracy......................................................................... 545
19.9 Usage Note........................................................................................................................ 546
Rev. 5.00 May 29, 2006 page xxxii of xlviii
18.5.2 Port E Data Register (PEDR)............................................................................... 516
18.6.1 Register Description............................................................................................. 517
18.6.2 Port F Data Register (PFDR) ............................................................................... 518
18.7.1 Register Description............................................................................................. 519
18.7.2 Port G Data Register (PGDR) .............................................................................. 520
18.8.1 Register Description............................................................................................. 521
18.8.2 Port H Data Register (PHDR) .............................................................................. 522
18.9.1 Register Description............................................................................................. 523
18.9.2 Port J Data Register (PJDR)................................................................................. 524
18.10.1 Register Description............................................................................................. 525
18.10.2 SC Port Data Register (SCPDR) .......................................................................... 526
19.3.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 532
19.3.2 A/D Control/Status Register (ADCSR) ............................................................... 533
19.3.3 A/D Control Register (ADCR) ............................................................................ 536
19.5.1 Word Access ........................................................................................................ 538
19.5.2 Longword Access................................................................................................. 538
19.6.1 Single Mode (MULTI = 0) .................................................................................. 539
19.6.2 Multi Mode (MULTI = 1, SCN = 0).................................................................... 540
19.6.3 Scan Mode (MULTI = 1, SCN = 1) ..................................................................... 542
19.6.4 Input Sampling and A/D Conversion Time ......................................................... 543
19.6.5 External Trigger Input Timing............................................................................. 545
19.9.1 Setting Analog Input Voltage .............................................................................. 546
19.9.2 Processing of Analog Input Pins.......................................................................... 547
19.9.3 Access Size and Read Data.................................................................................. 548
.................................................................................. 529