HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 266

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Bus State Controller (BSC)
The example in figure 8.13 shows the basic timing. To connect low-speed synchronous DRAM,
the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV
command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the
RCD bit in MCR, with a values of 0 to 3 specifying 1 to 4 cycles, respectively. In case of 2 or
more cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is
inserted between the Tr cycle and the Tc cycle. The number of cycles from READ and READA
command output cycles Tc1-Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3
cycles independently for areas 2 and 3 by means of A2W1 and A2W0 or A3W1 and A3W0 in
WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency
cycles.
Rev. 5.00 May 29, 2006 page 216 of 698
REJ09B0146-0500
CKIO
Address
upper bits
A12 or A11 *
Address
lower bits *
CS2 or CS3
RASx
CASx
RD/WR
DQMxx
D31 to D0
BS
Notes: 1.
2.
2
Command bit
Column address
1
Figure 8.13 Basic Timing for Synchronous DRAM Burst Read
Tr
Tc1
Tc2/Td1
Tc3/Td2
Tc4/Td3
Td4
Tpc