HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 344

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 Direct Memory Access Controller (DMAC)
Compare Match Timer Control/Status Register (CMCSR)
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the
occurrence of compare matches, and establishes the clock used for incrementation.
Note:
Rev. 5.00 May 29, 2006 page 294 of 698
REJ09B0146-0500
Bit
15 to 8
7
6
5 to 2
1
0
* The only value that can be written is 0 to clear the flag.
Bit Name
—
CMF
—
—
CKS1
CKS0
Initial Value
All 0
0
0
0
0
0
R/W
R
R/(W) * Compare match flag
R/W
R
R/W
R/W
Description
Reserved
These bits always read as 0. The write value
should always be 0.
This flag indicates whether CMCNT and CMCOR
values have matched or not.
0: CMCNT and CMCOR values have not matched
1: CMCNT and CMCOR values have matched
Reserved
Both read and write are available. The write value
should always be 0.
Reserved
These bits always read as 0. The write value
should always be 0.
Clock select 1 and 0
These bits select the clock input to the CMCNT
from among the four clocks obtained by dividing
the peripheral clock (P ). When the STR0 bit of
the CMSTR is set to 1, the CMCNT begins
incrementing with the clock selected by CKS1 and
CKS0.
00: P /4
01: P /8
10: P /16
11: P /64
Clearing condition: Write 0 to CMF after
reading CMF = 1