HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 118

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 Memory Management Unit (MMU)
3.4.4
When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of
virtual addresses are mapped onto a single physical address, the same physical address data will be
recorded in a number of cache entries, and it will not be possible to guarantee data congruity. The
reason why this problem only occurs when using a 1-kbyte page is explained below with reference
to figure 3.9.
To achieve high-speed operation of the SH7706 cache, an index number is created using virtual
address bits 11 to 4. When a 4-kbyte page is used, virtual address bits 11 to 4 are included in the
offset, and since they are not subject to address translation, they are the same as physical address
bits 11 to 4. In cache-based address comparison and recording in the address array, since the cache
tag address is a physical address, physical address bits 31 to 10 are recorded.
When a 1-kbyte page is used, also, a cache index number is created using virtual address bits 11 to
4. However, in case of a 1-kbyte page, virtual address bits (11, 10) are subject to address
translation and therefore may not be the same as physical address bits 11 and 10. Consequently,
the physical address is recorded in a different entry from that of the index number indicated by the
physical address in the cache address array.
For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following
translation has been performed are recorded in two TLBs:
Virtual address 1 is recorded in cache entry H'00, and virtual address 2 in cache entry H'C0. Since
two virtual addresses are recorded in different cache entries despite the fact that the physical
addresses are the same, memory inconsistency will occur as soon as a write is performed to either
virtual address. Therefore, when recording a 1-kbyte TLB entry, if the physical address is the same
as a physical address already used in another TLB entry, it should be recorded in such a way that
physical address bits (11, 10) are the same.
Rev. 5.00 May 29, 2006 page 68 of 698
REJ09B0146-0500
Virtual address 1 H'00000000
Virtual address 2 H'00000C00
Avoiding Synonym Problems
physical address H'00000C00
physical address H'00000C00