HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 48

IC SUPERH MPU ROMLESS 176LQFP

HD6417706F133

Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417706F133

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Table 10.3
Section 12 Timer Unit (TMU)
Table 12.1
Table 12.2
Section 13 Realtime Clock (RTC)
Table 13.1
Table 13.2
Section 14 Serial Communication Interface (SCI)
Table 14.1
Table 14.2
Table 14.3
Table 14.4
Table 14.5
Table 14.6
Table 14.7
Table 14.8
Table 14.9
Table 14.10 Serial Communication Formats (Asynchronous Mode) ......................................... 393
Table 14.11 Receive Error Conditions and SCI Operation ........................................................ 401
Table 14.12 SCI Interrupt Sources ............................................................................................. 417
Table 14.13 SCSSR Status Flags and Transfer of Receive Data................................................ 418
Section 15 Smart Card Interface
Table 15.1
Table 15.2
Table 15.3
Table 15.4
Table 15.5
Table 15.6
Table 15.7
Table 15.8
Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.1
Table 16.2
Table 16.3
Rev. 5.00 May 29, 2006 page xlvi of xlviii
Examples of Bit Rate B (Bit/s) for SCBRR Settings (n
Register Set Values and SCK Pin......................................................................... 433
Available Combination of Clock Mode and FRQCR Values................................. 308
Pin Configuration ................................................................................................... 325
TMU Interrupt Sources .......................................................................................... 338
RTC Pin Configuration .......................................................................................... 341
Recommended Oscillator Circuit Constants (Recommended Values) ................... 360
SCI Pins 367
SCSMR Settings..................................................................................................... 383
Bit Rates and SCBRR Settings in Asynchronous Mode ........................................ 384
Bit Rates and SCBRR Settings in Clock Synchronous Mode ................................ 387
Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)............................................................................................ 388
Maximum Bit Rates during External Clock Input (Asynchronous Mode) ............. 389
Maximum Bit Rates during External Clock Input (Clock Synchronous Mode)..... 389
Serial Mode Register Settings and SCI Communication Formats.......................... 391
SCSMR and SCSCR Settings and SCI Clock Source Selection ............................ 391
Pin Configuration ................................................................................................... 423
Register Settings for the Smart Card Interface....................................................... 429
Relationship of n to CKS1 and CKS0 .................................................................... 431
Examples of SCBRR Settings for Bit Rate B (Bit/s) (n
Maximum Bit Rates for Frequencies (Smart Card Interface Mode) ...................... 432
Smart Card Mode Operating State and Interrupt Sources ...................................... 437
SCIF Pins................................................................................................................ 445
SCSMR2 Settings................................................................................................... 460
Bit Rates and SCBRR2 Settings............................................................................. 461
0).................................. 431
0).................................. 432

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