HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 426

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Serial Communication Interface (SCI)
14.3.7
The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and
status flags that indicate SCI operating state.
The CPU can always read and write the SCSSR, but cannot write 1 in the status flags (TDRE,
RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
Rev. 5.00 May 29, 2006 page 376 of 698
REJ09B0146-0500
Bit
7
6
Bit Name
TDRE
RDRF
Serial Status Register (SCSSR)
Initial Value
1
0
R/W
R/(W) * Transmit Data Register Empty
R/(W) * Receive Data Register Full
Description
Indicates that the SCI has loaded transmit data from
the SCTDR into the SCTSR and new serial transmit
data can be written in the SCTDR.
0: SCTDR contains valid transmit data
1: SCTDR does not contain valid transmit data
Indicates that SCRDR contains received data.
0: SCRDR does not contain valid received data
1: SCRDR contains valid received data
Note: The SCRDR and RDRF are not affected by
[Clearing condition]
TDRE is read as 1, then written to with 0.
[Setting conditions]
[Clearing conditions]
1. The chip is reset or enters standby mode.
2. RDRF is read as 1, then written to with 0.
[Setting condition]
Serial data is received normally and transferred
from SCRSR to SCRDR.
1. The chip is reset or enters standby mode.
2. TE bit in the serial control register (SCSCR) is 0.
3. SCTDR contents are loaded into SCTSR, so
new data can be written in SCTDR.
detection of receive errors or by clearing of the
RE bit to 0 in the serial control register. They
retain their previous contents. If RDRF is still set
to 1 when reception of the next data ends, an
overrun error (ORER) occurs and the received
data is lost.