HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 145

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.4.3
C. When a privileged instruction in a delay slot is decoded in user mode
User break point trap
DMA Address error
A. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
B. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
NMI
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the
instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL,
MD, and RB bits in SR are set to 1 and a branch occurs to PC
undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed.
Conditions: When a break condition set in the user break point controller is satisfied
Operations: When a post-execution break occurs, the PC of the instruction immediately
after the instruction that set the break point is set in the SPC. If a pre-execution break
occurs, the PC of the instruction that set the break point is set in the SPC. SR when the
break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to PC
for more information.
Conditions: When corresponded to the following items.
4n + 3)
Operations: The PC of the instruction immediately after the instruction executed before the
exception occurs is saved to the SPC. SR when the exception occurs is saved to SSR.
H'5C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs
to PC
Conditions: NMI pin edge detection
Operations: The PC and SR after the instruction that receives the interrupt are saved to the
SPC and SSR, respectively. H'01C0 is set to INTEVT and INTEVT2. The BL, MD, and
RB bits of the SR are set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is
not masked by SR.IMASK and received with top priority when the SR's BL bit in SR is 0.
When the BL bit is 1, the interrupt is masked. When BLMSK in ICRI is a logic zero and
not masked when BLMSK in ICRI is a logic one. See section 6, Interrupt Controller
(INTC), for more information.
Interrupts
VBR + H'0100.
VBR + H'0100. See section 7, User Break Controller,
Rev. 5.00 May 29, 2006 page 95 of 698
Section 4 Exception Processing
VBR + H'0100. When an
REJ09B0146-0500