HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 498

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Bit
4
3
2
Rev. 5.00 May 29, 2006 page 448 of 698
REJ09B0146-0500
Bit Name
O/E
STOP
—
Initial
Value
0
0
0
R/W
R/W
R/W
R
Description
Parity Mode
Selects even or odd parity when parity bits are added and
checked. The O/E setting is used only when the PE is set
to 1 to enable parity addition and check. The O/E setting is
ignored when parity addition and check is disabled.
0: Even parity.
1: Odd parity.
Stop Bit Length
Selects one or two bits as the stop bit length.
In receiving, only the first stop bit is checked, regardless of
the STOP bit setting. If the second stop bit is 1, it is treated
as a stop bit, but if the second stop bit is 0, it is treated as
the start bit of the next incoming character.
0: One stop bit.
1: Two stop bits.
Reserved
This bit is always read as 0. The write value should always
be 0.
Note: In transmitting, a single bit of 1 is added at the
end of each transmitted character.
Note: In transmitting, two bits of 1 are added at the end
of each transmitted character.
Note: If even parity is selected, the parity bit is added to
transmit data to make an even number of 1s in the
transmitted character and parity bit combined. Receive
data is checked to see if it has an even number of 1s in
the received character and parity bit combined.
Note: If odd parity is selected, the parity bit is added to
transmit data to make an odd number of 1s in the
transmitted character and parity bit combined. Receive
data is checked to see if it has an odd number of 1s in
the received character and parity bit combined.