HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 334

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 Direct Memory Access Controller (DMAC)
Bus Mode and Channel Priority Order: When a given channel 1 is transferring in the burst
mode and there is a transfer request to a channel 0 with a higher priority, the transfer of channel 0
will begin immediately.
At this time, if the priority is set in the fixed mode (CH0 > CH1), the channel 1 transfer will
continue when the channel 0 transfer has completely finished, even if channel 0 is operating in the
cycle-steal mode or in the burst mode.
If the priority is set in the round-robin mode, channel 1 will begin operating again after channel 0
completes the transfer of one transfer unit, even if channel 0 is in the cycle-steal mode or in the
burst mode. The bus will then switch between the two in the order channel 1, channel 0, channel 1,
channel 0.
Even if the priority is set in the fixed mode or in the round-robin mode, it will not give the bus to
the CPU since channel 1 is in the burst mode. This example is illustrated in figure 9.16.
9.4.5
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycles is
controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 8, Bus State Controller (BSC).
DREQ
DREQ
DREQ
DREQ Pin Sampling Timing: In the external request mode, the DREQ pin is sampled by clock
pulse (CKIO) falling edge or low level detection. When DREQ input is detected, a DMAC bus
cycle is generated and DMA transfer is performed, at the earliest, three states later.
The second and subsequent DREQ sampling operations are started two cycles after the first
sample.
Rev. 5.00 May 29, 2006 page 284 of 698
REJ09B0146-0500
Notes:
CPU
Number of Bus Cycle States and DREQ
CPU
1. Cycle-steal mode
2. Burst mode
Figure 9.16 Bus State when Multiple Channels Are Operating
DMAC
CH1
DMAC CH1
Burst mode
DMAC
CH1
(Priority Level Is Round-Robin Mode)
DMAC
CH0
*
1
DMAC CH0 and CH1
Round-robin mode in
DREQ Pin Sampling Timing
DREQ
DREQ
DMAC
CH1
*
2
DMAC
CH0
*
1
DMAC
CH1
DMAC CH1
Burst mode
DMAC
CH1
CPU
CPU