HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 21

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
Section 22 Power-
Down Modes
Table 22.1 Power-
Down Modes
22.3.3 Module
Standby Function
Transition to Module
Standby Function
24.3.1 Clock Timing
Figure 24.4 Power-
On Oscillation Settling
Time
Page
568
576
615
Revision (See Manual for Details)
Table amended and note 5 added
Note: 5. If the realtime clock (RTC) is set to module standby
mode (bit 1 in standby control register (STBCR) set to 1) before
any register in the RTC, SCI, or TMU is accessed, registers in
the serial communication interface (SCI) or timer unit (TMU)
may not be read properly. To avoid this problem, access (read
or write) any register in the RTC, SCI, or TMU once or more
before setting the RTC to module standby mode.
Description added
If the realtime clock (RTC) is set to module standby mode (bit 1
in standby control register (STBCR) set to 1) before any
register in the RTC, SCI, or TMU is accessed, registers in the
serial communication interface (SCI) or timer unit (TMU) may
not be read properly. To avoid this problem, access (read or
write) any register in the RTC, SCI, or TMU once or more
before setting the RTC to module standby mode.
Figure amended
Mode
Module
standby
function
CKIO,
internal clock
V
V
V
V
RESETP
CC
CC
CC
CC
– RTC
– PLL1
– PLL2
Transition
Conditions
Set MSTP bit of
STBCR to 1 *
5
V
CC
CPG
Runs Runs
min
CPU
*
4
Rev. 5.00 May 29, 2006 page xix of xlviii
CPU
Reg-
ister
Held
On-Chip
Memory
Held
State
t
OSC1
On-Chip
Peripheral
Modules
Specified
module
halts
Pins
*
2
External
Memory
Refresh
Canceling
Procedure
1. Clear MSTP
2. Power-on
bit to 0
reset