HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 337

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(High active)
(High active)
(RD output)
(High active)
(RD output)
Bus cycle
Figure 9.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed)
Bus cycle
Bus cycle
DREQ
DRAK
DACK
DREQ
CKIO
DRAK
DACK
DREQ
DRAK
DACK
CKIO
CKIO
1st sampling
Note: When a DREQ falling edge is detected, DREQ must be high for at least one cycle before the sampling point.
1st sampling
1st sampling
CPU
CPU
CPU
Figure 9.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles)
2nd sampling is performed,
but since DREQ is high,
per-cycle sampling starts
2nd sampling
2nd sampling is performed,
but since there is no DREQ falling edge,
per-cycle sampling starts
DMAC(Read)
DMAC(Read)
DMAC(Read)
High
Figure 9.22 Burst Mode, Level Input
2nd sampling
High
DMAC(Write)
DMAC(Write)
2nd sampling
DMAC(Write)
Section 9 Direct Memory Access Controller (DMAC)
3rd sampling is performed,
but since DREQ is high,
per-cycle sampling starts
3rd sampling is performed,
but since there is no DREQ falling edge,
per-cycle sampling starts
CPU
CPU
3rd sampling
Rev. 5.00 May 29, 2006 page 287 of 698
DMAC(Read)
DMAC(Read)
DMAC(Read)
High
3rd sampling
High
DMAC(Write)
REJ09B0146-0500
DMAC(Write)
DMAC(Write)
3rd sampling
DMAC(Read)
CPU
CPU