HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 339

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Even if the transfer data size is 8, 16, or 32 bits, a reload function can be executed.
DMATCR_2, which specifies a transfer count, decrements 1 each time a transfer ends regardless
of whether a reload function is on or off. Consequently, be sure to specify the value multiple of
four in DMATCR_2 when the reload function is on. Specifying other values does not guarantee
the operation.
Though the counters that count transfers of four times for the reload function are reset by clearing
the DME bit in DMAOR or the DE bit in CHCR_2, by setting the transfer end flag (TE bit in
CHCR_2) by a DMAC address error, or by inputting NMI, besides by resets, the SAR_2, DAR_2,
DMATCR_2 registers are not reset. Therefore, if these sources are generated, the counters that are
initialized and are not initialized exist in the DMAC; malfunction will be caused by restarting the
DMAC in that state. Consequently, if these sources occur except for setting the TE bit during the
usage of the reload function, set SAR_2, DAR_2, and DMATCR_2 again.
address bus
data bus
Internal
Internal
CK
Figure 9.25 Timing Chart of Source Address Reload Function
First transfer of
SAR_2
DAR_2 output
SAR_2 output
channel 2
DAR_2
SAR_2 data
SAR_2+2
Second transfer
SAR_2+2 output
DAR_2 output
DAR_2
Section 9 Direct Memory Access Controller (DMAC)
SAR_2+2 data
SAR_2+4
SAR_2+4 output
DAR_2 output
Third transfer
Rev. 5.00 May 29, 2006 page 289 of 698
DAR_2
SAR_2+4 data
SAR_2+6
SAR_2+6 output
Fourth transfer
DAR_2 output
DAR_2
SAR_2+6 data
REJ09B0146-0500
SAR_2 reload
SAR_2 output
DAR_2 output
Fifth transfer
SAR_2