HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 152

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 5 Cache
5.2.2
Cache control register 2 (CCR2) enables or disables the cache locking mechanism. This register
setting is valid only in cache locking mode. Cache locking mode is enabled when the cache
locking bit (bit 12) of the status register (SR) is set to 1, and disabled when it is cleared to 0.
If a cache miss occurs during prefetch instruction (PREF) execution in cache locking mode, one
line size of data pointed by Rn is loaded into the cache according to the W3LOAD, W3LOCK,
W2LOAD, and W2LOCK bit settings of CCR2 (bits 9, 8, 1, and 0). Table 5.2 shows the
relationship between each bit setting and the way to be replaced when the prefetch instruction is
executed. On the other hand, if a cache hit occurs during prefetch instruction (PREF) execution, no
data is loaded into the cache and entries that have been valid in the cache are maintained. For
instance, if one line size of data pointed by Rn exists at way 0, and if the prefetch instruction is
executed while the cache lock, W3LOAD, and W3LOCK are set to 1s, a cache hit occurs and data
is not brought to way 3.
When a cache is accessed by other than the prefetch instruction in cache locking mode, the ways
to be replaced are controlled by the W3LOCK and W2LOCK bit settings. Table 5.3 shows the
relationship between CCR2 bit settings and the way to be replaced.
A program to modify the CCR2 contents should be placed at an address area whose data is not
cached.
Rev. 5.00 May 29, 2006 page 102 of 698
REJ09B0146-0500
Bit
31 to 10
9
8
7 to 2
Cache Control Register 2 (CCR2)
Bit Name
W3LOAD
W3LOCK
Initial Value
All 0
0
0
All 0
R/W
R
W
W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
W3LOAD: Way 3 load
W3LOCK: Way 3 Lock
When W3LOACK = 1 & W3LOAD = 1 & SR.CL is
1, the prefetched data will always be loaded into
Way3. In all other conditions, the prefetched data
will be loaded into the way pointed by LRU.
Reserved
These bits are always read as 0. The write value
should always be 0.