HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 503

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
7
Bit Name
ER
Initial
Value
0
R/W
R/(W) * Receive error
Section 16 Serial Communication Interface with FIFO (SCIF)
Description
Indicates that a framing error or a parity error, when
receiving data containing parity bits, has occurred.
0: Receive is in progress, or receive is normally
1: A framing error or a parity error has occurred during
Notes: 1. Clearing the RE bit to 0 in SCSCR2 does not
[Clearing conditions]
1. The chip is power-on reset or enters standby mode.
2. ER is read as 1, then written to with 0.
receiving.
ER is set to 1 when the stop bit is 0 after checking
whether or not the last stop bit of the received data is 1
at the end of one-data receive * , or when the total
number of 1's in the received data and in the parity bit
does not match the even/odd parity specification
specified by the O/E bit of the SCSMR.
[Setting conditions]
1. The stop bit is 0 after checking whether or not the
2. The total number of 1's in the received data and in
completed. *
last stop bit of the received data is 1 at the end of
one-data receive. *
the parity bit does not match the even/odd parity
specification specified by the O/E bit of the SCSMR2.
2. n the stop mode, only the first stop bit is
affect the ER bit, which retains its previous
value. Even if a receive error occurs, the
received data is transferred to SCFRDR2 and
the receive operation is continued. Whether or
not the data read from SCRDR2 includes a
receive error can be detected by the FER and
PER bits of SCSSR2.
checked; the second stop bit is not checked.
1
Rev. 5.00 May 29, 2006 page 453 of 698
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REJ09B0146-0500