HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 483

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 15.7 Register Set Values and SCK Pin
Notes: 1. The SCK0 output state changes as soon as the CKE0 bit is modified. The CKE1 bit
15.4.6
Initialization: Initialize the SCI using the following procedure before sending or receiving data.
Initialization is also required for switching from transmit mode to receive mode or from receive
mode to transmit mode. Figure 15.5 shows an example of initialization process flowchart.
1. Clear TE and RE in SCSCR to 0.
2. Clear error flags FER/ERS, PER, and ORER to 0 in SCSSR.
3. Set the C/A bit, parity bit (O/E bit), and baud rate generator select bits (CKS1 and CKS0 bits)
4. Set the SMIF, SDIR, and SINV bits in SCSCMR. When the SMIF bit is set to 1, the TxD and
5. Set the value corresponding to the bit rate in SCBRR.
6. Set the clock source select bits (CKE1 and CKE0 bits) in SCSCR. Clear the TIE, RIE, TE, RE,
7. After waiting at least 1 bit, set the TIE, RIE, TE, and RE bits in SCSCR. Do not set the TE and
Setting
1 *
2 *
3 *
1
2
2
in SCSMR. At this time also clear the CHR and MP bits to 0 and set the STOP and PE bits to
1.
RxD pins both switch from ports to SCI pins and become high impedance.
MPIE, and TEIE bits to 0. When the CKE0 bit is set to 1, a clock is output from the SCK pin.
RE bits simultaneously unless performing self-diagnosis.
2. The clock duty remains constant despite stopping and starting of the clock by
Data Transmission and Reception
SMIF
1
1
1
1
1
1
should be cleared to 0.
modification of the CKE0 bit.
Register Value
C/A A A A
0
0
1
1
1
1
CKE1
0
0
0
0
1
1
CKE0
0
1
0
1
0
1
Output
Port
Low output
High output
Rev. 5.00 May 29, 2006 page 433 of 698
State
Determined by setting of port register
SCP1MD1 and SCP1MD0 bits
SCK0 (serial clock) output state
Low output state
SCK0 (serial clock) output state
High output state
SCK0 (serial clock) output state
Section 15 Smart Card Interface
SCK Pin
REJ09B0146-0500