HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 582

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 A/D Converter (ADC)
19.3.1
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte (bits 15 to 8) of the A/D data register. The lower 2 bits are stored in the lower byte (bits 7 and
6). Bits 5 to 0 of an A/D data register are reserved bits that always read 0. For the reading of the
data, see section 19.4, Bus Master Interface, and section 19.9.3, Access Size and Read Data. Table
19.2 indicates the pairings of analog input channels and A/D data registers.
Table 19.2 Analog Input Channels and A/D Data Registers
Rev. 5.00 May 29, 2006 page 532 of 698
REJ09B0146-0500
Bit
15 to 6
5 to 0
Analog Input Channel
Group 0
AN0
AN1
AN2
AN3
A/D Data Registers A to D (ADDRA to ADDRD)
Bit Name
AD9 to AD0
Initial Value
All 0
All 0
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
R/W
R
R
Description
Bit data (10 bits)
Reserved
These bits are always read as 0.