HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 195

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.2.7
BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified
by BDRB.
Notes: n = 31 to 0
7.2.8
Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the
break conditions of channel B.
Bit
31 to 0
Bit
15 to 8
7
6
Specify an operand size when including the value of the data bus in the break condition.
When a byte size is selected as a break condition, the break data must be set in bits 15 to 8
in BDRB for an even break address and bits 7 to 0 for an odd break address.
Break Data Mask Register B (BDMRB)
Break Bus Cycle Register B (BBRB)
Bit Name
—
CDB1
CDB0
Bit Name
BDMB31 to
BDMB0
Initial Value
All 0
0
0
Initial Value R/W
All 0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. These bits are
always read as 0.
CPU Cycle/DMAC Cycle Select B
Select the CPU cycle or DMAC cycle as the bus
cycle of the channel B break condition.
00: Condition comparison is not performed
X1: The break condition is the CPU cycle
10: The break condition is the DMAC cycle
Description
Break Data Mask
0: Break data BDBn of channel B is included in the
1: Break data BDBn of channel B is masked and is
break condition
not included in the break condition
Rev. 5.00 May 29, 2006 page 145 of 698
Section 7 User Break Controller
REJ09B0146-0500