HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 46

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Section 3 Memory Management Unit (MMU)
Table 3.1
Section 4 Exception Processing
Table 4.1
Table 4.2
Table 4.3
Section 5 Cache
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Section 6 Interrupt Controller (INTC)
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Rev. 5.00 May 29, 2006 page xliv of xlviii
Initial Register Values ............................................................................................ 15
Addressing Modes and Effective Addresses .......................................................... 23
Instruction Formats ................................................................................................ 27
Classification of Instructions.................................................................................. 30
Data Transfer Instructions ...................................................................................... 34
Arithmetic Instructions........................................................................................... 36
Logic Operation Instructions.................................................................................. 39
Shift Instructions .................................................................................................... 40
Branch Instructions ................................................................................................ 41
System Control Instructions ................................................................................... 42
Instruction Code Map............................................................................................. 46
Access States Designated by D, C, and PR Bits..................................................... 65
Exception Event Vectors ........................................................................................ 82
Exception Codes..................................................................................................... 85
Types of Reset........................................................................................................ 92
LRU and Way Replacement................................................................................... 100
Way to be Replaced when Cache Miss Occurs during PREF Instruction
Execution................................................................................................................ 103
Way to be Replaced when Cache Miss Occurs during Execution of Instruction
Other than PREF Instruction .................................................................................. 104
LRU and Way Replacement (When W2LOCK = 1) .............................................. 104
LRU and Way Replacement (When W3LOCK = 1) .............................................. 104
LRU and Way Replacement (When W2LOCK = 1 and W3LOCK = 1) ............... 104
Pin Configuration ................................................................................................... 115
IRL3 to IRL0 Pins and Interrupt Levels................................................................. 117
Interrupt Exception Handling Sources and Priority (IRQ Mode)........................... 119
Interrupt Exception Handling Sources and Priority (IRL Mode) ........................... 121
Interrupt Level and INTEVT Code ........................................................................ 123
Interrupt Request Sources and IPRA to IPRE ........................................................ 124
Tables