HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 413

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

This LSI has an on-chip serial communication interface (SCI) that supports both asynchronous and
clock synchronous serial communication. It also has a multiprocessor communication function for
serial communication among two or more processors. A block diagram of SCI is shown in figure
14.1, and the I/O ports are shown in figures 14.2 to 14.4.
14.1
The SCI has the following features.
Selectable from asynchronous or clock synchronous as the serial communications mode
Asynchronous mode:
Clock synchronous mode:
Full duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. Both sections use double buffering, so continuous data transfer is possible in
both the transmit and receive directions.
Serial data communications are synched by start-stop in character units. The SCI can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. It can also communicate with two or more other
processors using the multiprocessor communication function. There are 12 selectable serial
data communication formats.
Data length: Seven or eight bits
Stop bit length: One or two bits
Parity: Even, odd, or none
Multiprocessor bit: 1 or 0
Receive error detection: Parity, overrun, and framing errors
Break detection: By reading the RxD0 pin level directly from the port Serial
communication port data register (SCPDR) when a framing error occurs
Serial data communication is synchronized with a clock signal. The SCI can communicate
with other chips having a clock synchronous communication function. One serial data
communication format is available.
Data length: Eight bits
Receive error detection: Overrun errors
Section 14 Serial Communication Interface (SCI)
Feature
Section 14 Serial Communication Interface (SCI)
Rev. 5.00 May 29, 2006 page 363 of 698
REJ09B0146-0500