HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 129

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.6.3
Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry's
V bit. R0 specifies the write data and R1 specifies the address.
Reading the Data of a Specific Entry: This example reads the data section of a specific TLB
entry. The bit order indicated in the data field in figure 3.14 (2) is read. R0 specifies the address
and the data section of a selected entry is read to R1.
3.7
3.7.1
Instructions that manipulate the MD or BL bit in register SR (the LDC Rm, SR instruction, LDC
@Rm+, SR instruction, and RTE instruction) and the following instruction, or the LDTLB
instruction, should be used with the TLB disabled or in a fixed physical address space (the P1 or
P2 space).
; R0=H'1547 381C
; MMUCR.IX=0
; VPN(31–17)=B'000 1010 1010 0011
; corresponding entry association is made from the entry selected by
; the VPN(16–12)=B'1 0011 index, the V bit of the hit way is cleared to
; 0,achieving invalidation.
MOV.L
; R0 H'F300 4300
; MOV.L @R0,R1
Usage Note
Usage Examples
Use of Instructions Manipulating MD and BL Bits in SR
R0,@R1
R1=H'F201 3000
VPN(16-12)=B'0 0100
VPN(11–10)=B'10
Section 3 Memory Management Unit (MMU)
Way 3
Rev. 5.00 May 29, 2006 page 79 of 698
ASID=B'0001 1100
REJ09B0146-0500