HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 168

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 6 Interrupt Controller (INTC)
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that
no transient level on the IRL pin change is detected. In the software standby mode, as the
peripheral clock is stopped, noise cancellation is performed using the 32-kHz clock for the RTC
instead. Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be
performed in software standby mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt processing starts. If the level is not retained, correct operation is not guaranteed.
However, the priority level can be changed to a higher one.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRL interrupt
processing.
6.3.4
On-chip peripheral module interrupts are generated by the following eight modules:
Not every interrupt source is assigned a different interrupt vector, but sources are reflected in the
interrupt event registers (INTEVT and INTEVT2), so it is easy to identify sources by branching
with the INTEVT or INTEVT2 register value as an offset.
The priority level (from 0 to 15) can be set for each module except for H-UDI by writing to the
interrupt priority setting registers A, B and E (IPRA, IPRB and IPRE). The priority level of H-
UDI interrupt is 15 (fixed).
The interrupt mask bits (I3 to I0) of the SR are not affected by the on-chip peripheral module
interrupt processing.
TMU and RTC interrupts can restore the chip from the software standby state when the relevant
interrupt level is higher than I3 to I0 in the SR (but only when the RTC 32-kHz oscillator is used).
Rev. 5.00 May 29, 2006 page 118 of 698
REJ09B0146-0500
Timer unit (TMU)
Realtime clock (RTC)
Serial communication interface (SCI, SCIF)
Bus state controller (BSC)
Watchdog timer (WDT)
Direct memory access controller (DMAC)
A/D converter (ADC)
User debugging interface (H-UDI)
On-Chip Peripheral Module Interrupts