HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 267

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 8.14 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10, and
TPC is set to 1.
The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal space access, is
asserted in each of cycles Td1 to Td4 in a synchronous DRAM cycle. When a burst read is
performed, the address is updated each time CAS is asserted. As the unit of burst transfer is 16
bytes, address updating is performed for A3 and A2 only (A3, A2, and A1 for a 16-bit bus width).
The order of access is as follows: in a fill operation in the event of a cache miss, the missed data is
read first, then 16-byte boundary data including the missed data is read in wraparound mode.
CKIO
CS2 or CS3
RASx
CASx
RD/WR
DQMxx
D31 to D0
BS
Notes: 1.
Address
upper bits
A12 or A11 *
Address
lower bits *
2.
2
Command bit
Column address
Figure 8.14 Synchronous DRAM Burst Read Wait Specification Timing
1
Tr
Trw
Tc1
Tc2
Tc3/Td1
Rev. 5.00 May 29, 2006 page 217 of 698
Section 8 Bus State Controller (BSC)
Tc4/Td2
Td3
REJ09B0146-0500
Td4
Tpc