HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 624

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 22 Power-Down Modes
22.3.2
Transition to Software Standby Mode
To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The
chip moves from the program execution state to software standby mode. In software standby
mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-
chip supporting modules as well. The clock output from the CKIO pin also halts. CPU and cache
register contents are held, but some on-chip supporting modules are initialized. Table 22.3 lists the
states of registers in software standby mode.
Table 22.3 Register States in Software Standby Mode
The procedure for moving to software standby mode is as follows:
1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. Set the
2. After the STBY bit in the STBCR register is set to 1, a SLEEP instruction is executed.
3. Software standby mode is entered and the clocks within the chip are halted. The STATUS1 pin
Canceling Software Standby Mode
Standby mode is canceled by an interrupt (NMI, IRQ *
a reset.
Rev. 5.00 May 29, 2006 page 574 of 698
REJ09B0146-0500
Module
Interrupt controller (INTC)
On-chip clock pulse generator
(CPG)
User Break controller (UBC)
Bus state controller (BSC)
Timer unit (TMU)
Realtime clock (RTC)
A/D converter (ADC)
D/A converter (DAC)
WDT's timer counter (WTCNT) and the CKS2 to CKS0 bits of the WTCSR register to
appropriate values to secure the specified oscillation settling time.
output goes low and the STATUS0 pin output goes high.
Software Standby Mode
Registers Initialized
—
—
—
—
TSTR register
—
All registers
—
1
, IRL *
1
, or on-chip supporting module) *
Registers Retaining Data
All registers
All registers
All registers
All registers
Registers other than TSTR
All registers
—
All registers
2
or