HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 198

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 7 User Break Controller
Rev. 5.00 May 29, 2006 page 148 of 698
REJ09B0146-0500
Bit
15
14
13
12
Bit Name
SCMFCA
SCMFCB
SCMFDA
SCMFDB
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
CPU Condition Match Flag A
When the CPU bus cycle condition in the break
conditions set for channel A is satisfied, this flag
is set to 1 (not cleared to 0). In order to clear this
flag, write 0 into this bit.
0: The CPU cycle condition for channel A does
1: The CPU cycle condition for channel A
CPU Condition Match Flag B
When the CPU bus cycle condition in the break
conditions set for channel B is satisfied, this flag
is set to 1 (not cleared to 0). In order to clear this
flag, write 0 into this bit.
0: The CPU cycle condition for channel B does
1: The CPU cycle condition for channel B
DMAC Condition Match Flag A
When the on-chip DMAC bus cycle condition in
the break conditions set for channel A is
satisfied, this flag is set to 1 (not cleared to 0). In
order to clear this flag, write 0 into this bit.
0: The DMAC cycle condition for channel A does
1: The DMAC cycle condition for channel A
DMAC Condition Match Flag B
When the on-chip DMAC bus cycle condition in
the break conditions set for channel B is
satisfied, this flag is set to 1 (not cleared to 0). In
order to clear this flag, write 0 into this bit.
0: The DMAC cycle condition for channel B does
1: The DMAC cycle condition for channel B
not match
matches
not match
matches
not match
matches
not match
matches