HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 351

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.7
1. CHCR_0 to CHCR_3 can be accessed in any data size. The DMA operation register
2. Before rewriting the RS0 to RS3 bits of CHCR_0 to CHCR_3, first clear the DE bit to 0 (when
3. Even when the NMI interrupt is input when the DMAC is not operating, the NMIF bit of the
4. When entering the standby mode, the DME bit in DMAOR must be cleared to 0 and the
5. The on-chip peripherals which DMAC can access are SCIF, A/D converter, D/A converter,
6. When starting up the DMAC, set CHCR_0 to CHCR_3 or DMAOR last. Specifying other
7. Even if the maximum number of transfers is performed in the same channel after the
8. When using the address reload function, specify the burst mode as a transfer mode. In the
9. When using the address reload function, set the value multiple of four in DMATCR_0 to
10. When detecting an external request at the falling edge, keep the external request pin high when
11. Do not access the space ranging from H'4000062 to H'400006F, which is not used in the
12. The WAIT signal is ignored in the following cases:
13. When the DMAC transfers data under conditions (1) or (2) below, the CPU may fetch an
(DMAOR) must be accessed in byte (eight bits) or word (16 bits); other registers must be
accessed in word (16 bits) or longword (32 bits).
rewriting CHCR, be sure to clear the DE bit to 0 in advance).
DMAOR will be set.
transfers accepted by the DMAC must end.
and I/O ports. Do not access the other peripherals by DMAC.
registers last does not guarantee normal operation.
DMATCR_0 to DMATCR_3 count reaches 0 and the DMA transfer ends normally, write 0 to
DMATCR_0 to DMATCR_3. Otherwise, normal DMA transfer may not be performed.
cycle-steal mode, normal DMA transfer may not be performed.
DMATCR_3. Specifying other values does not guarantee normal operation.
setting the DMAC.
DMAC. Accessing that space may cause malfunctions.
A. In 16-byte DMA transfer or dual addressing mode, or when writing data to the external
B. In 16-byte DMA transfer or single addressing mode, or when transferring data from an
unexpected instruction, resulting in program runaway, or the DMA may transfer the wrong
data.
(1) At wake-up from the sleep mode when operating with a clock ratio for I :B of other than
(2) The internal clock frequency division ratio bits (IFC[2:0]) in the frequency control register
address area
external device with DACK to the external address area
1:1.
(FRQCR) are modified.
Cautions
Section 9 Direct Memory Access Controller (DMAC)
Rev. 5.00 May 29, 2006 page 301 of 698
REJ09B0146-0500