HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 38

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 6 Interrupt Controller (INTC)
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Section 7 User Break Controller
Figure 7.1
Section 8 Bus State Controller (BSC)
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10
Figure 8.11
Figure 8.12
Figure 8.13
Figure 8.14
Figure 8.15
Figure 8.16
Figure 8.17
Figure 8.18
Figure 8.19
Figure 8.20
Figure 8.21
Figure 8.22
Figure 8.23
Figure 8.24
Figure 8.25
Figure 8.26
Figure 8.27
Figure 8.28
Figure 8.29
Figure 8.30
Rev. 5.00 May 29, 2006 page xxxvi of xlviii
INTC Block Diagram........................................................................................... 114
Example of IRL Interrupt Connection ................................................................. 117
Interrupt Operation Flowchart ............................................................................. 134
Example of Pipeline Operations when IRL Interrupt Is Accepted....................... 138
Block Diagram of User Break Controller ............................................................ 140
BSC Functional Block Diagram .......................................................................... 164
Corresponding to Logical Address Space and Physical Address Space .............. 167
Physical Space Allocation.................................................................................... 169
PCMCIA Space Allocation.................................................................................. 170
Basic Timing of Basic Interface........................................................................... 206
Example of 32-Bit Data-Width Static RAM Connection..................................... 207
Example of 16-Bit Data-Width Static RAM Connection..................................... 208
Example of 8-Bit Data-Width Static RAM Connection....................................... 208
Basic Interface Wait Timing (Software Wait Only) ............................................ 209
Basic Interface Wait State Timing
(Wait State Insertion by WAIT Signal WAITSEL = 1)....................................... 210
Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width) ....... 212
Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width) .......................... 213
Basic Timing for Synchronous DRAM Burst Read............................................. 216
Synchronous DRAM Burst Read Wait Specification Timing.............................. 217
Basic Timing for Synchronous DRAM Single Read ........................................... 218
Basic Timing for Synchronous DRAM Burst Write ............................................ 219
Basic Timing for Synchronous DRAM Single Write .......................................... 220
Burst Read Timing (No Precharge) ..................................................................... 223
Burst Read Timing (Same Row Address) ............................................................ 224
Burst Read Timing (Different Row Addresses) ................................................... 225
Burst Write Timing (No Precharge)..................................................................... 226
Burst Write Timing (Same Row Address) ........................................................... 227
Burst Write Timing (Different Row Addresses) .................................................. 228
Auto-Refresh Operation....................................................................................... 229
Synchronous DRAM Auto-Refresh Timing ........................................................ 230
Synchronous DRAM Self-Refresh Timing .......................................................... 231
Synchronous DRAM Mode Write Timing........................................................... 233
Burst ROM Wait Access Timing ......................................................................... 235
Burst ROM Basic Access Timing ........................................................................ 236
PCMCIA Space Allocation.................................................................................. 237