HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 382

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 Timer Unit (TMU)
12.3.5
TCNT counts down according to the input of a clock. The timer counters are 32-bit read/write
registers. The TMU has three timer counters, one for each channel.The clock input is selected
using the TPSC2 to TPSC0 bits in the TCR_0 to TCR_2.
When a TCNT count-down results in an underflow (H'00000000
flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is
simultaneously set in TCNT itself and the count-down continues from that value.
Because the internal bus for this LSI on-chip supporting modules is 16 bits wide, a time lag can
occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT counts
sequentially, this time lag can create discrepancies between the data in the upper and lower halves.
To correct the discrepancy, a buffer register is connected to TCNT so that upper and lower halves
are not read separately. The entire 32-bit data in TCNT can thus be read at once.
TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset; it is not initialized in
standby mode, and retains its contents.
12.3.6
The input capture register (TCPR_2) is a read-only 32-bit register built only into timer 2. Control
of TCPR_2 setting conditions due to the TCLK pin is affected by the input capture function bits
(ICPE1/ICPE2 and CKEG1/CKEG0) in TCR2. When a TCPR_2 setting indication due to the
TCLK pin occurs, the value of TCNT_2 is copied into TCPR_2.
TCNT_2 is not initialized by a power-on reset or manual reset, or in standby mode.
12.4
Each of three channels has a 32-bit timer counter (TCNT_0 to TCNT_2) and a 32-bit timer
constant register (TCOR_0 to TCOR_2). The TCNT counts down. The auto-reload function
enables synchronized counting and counting by external events. Channel 2 has an input capture
function.
Rev. 5.00 May 29, 2006 page 332 of 698
REJ09B0146-0500
Timer Counters 0 to 2 (TCNT_0 to TCNT_2)
Input Capture Register 2 (TCPR_2)
Operation
H'FFFFFFFF), the underflow