HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 76

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 CPU
Addressing
Mode
PC-relative
Immediate
Note: For the addressing modes below that use a displacement (disp), the assembler descriptions
Rev. 5.00 May 29, 2006 page 26 of 698
REJ09B0146-0500
in this manual show the value before scaling ( 1, 2, or 4) is performed according to the
operand size. This is done to clarify the operation of the LSI. Refer to the relevant
assembler notation rules for the actual assembler descriptions.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, Rn) ; GBR indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12 ; PC-relative
Instruction
Format
Rn
#imm:8
#imm:8
#imm:8
Effective Address Calculation Method
Effective address is sum of register PC and
Rn contents.
8-bit immediate data imm of TST, AND, OR,
or XOR instruction is zero-extended.
8-bit immediate data imm of MOV, ADD,
or CMP/EQ instruction is sign-extended.
8-bit immediate data imm of TRAPA
instruction is zero-extended and multiplied
by 4.
PC
R0
+
PC + R0
Calculation Formula
PC + Rn
—
—
—