HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 268

IC SUPERH MPU ROMLESS 176LQFP

HD6417706F133

Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417706F133

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Section 8 Bus State Controller (BSC)
Single Read
Figure 8.15 shows the timing when a single address read is performed. As the burst length is set to
1 in synchronous DRAM burst read/single write mode, only the required data is output.
Consequently, no unnecessary bus cycles are generated even when a cache-through area is
accessed.
Burst Write
The timing chart for a burst write is shown in figure 8.16. In this LSI, a burst write occurs only in
the event of cache write-back or 16-byte transfer by DMAC. In a burst write operation, following
the Tr cycle in which ACTV command output is performed, a WRIT command is issued in the
Rev. 5.00 May 29, 2006 page 218 of 698
REJ09B0146-0500
Figure 8.15 Basic Timing for Synchronous DRAM Single Read
CKIO
Address
upper bits
A12 or A11 *
Address
lower bits *
CS2 or CS3
RASx
CASx
RD/WR
DQMxx
D31 to D0
BS
Notes: 1.
2.
2
Command bit
Column address
1
Tr
Tc1
Td1
Tpc

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