HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 323

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Address Modes:
Dual Address Mode
In the dual address mode, both the transfer source and destination are accessed (selectable) by
an address. The source and destination can be located externally or internally. The dual address
mode has (1) direct address transfer mode and (2) indirect address transfer mode.
(1) In the direct address transfer mode, DMA transfer requires two bus cycles because data is
read from the transfer source in a data read cycle and written to the transfer destination in a
data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the
transfer between external memories as shown in figure 9.5, data is read to the DMAC from
one external memory in a data read cycle, and then that data is written to the other external
memory in a write cycle. Figures 9.6 to 9.8 show examples of the timing at this time.
Figure 9.5 Operation in the Direct Address Mode in the Dual Address Mode
The SAR value is an address, data is read from the transfer source module,
and the data is tempolarily stored in the DMAC.
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Data buffer
Data buffer
DMAC
DMAC
SAR
DAR
SAR
DAR
Second bus cycle
First bus cycle
Section 9 Direct Memory Access Controller (DMAC)
Rev. 5.00 May 29, 2006 page 273 of 698
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module
REJ09B0146-0500