HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 345

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Compare Match Counter (CMCNT)
The compare match counter (CMCNT) is a 16-bit register used as an up-counter.
When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR and the STR bit
of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the
CMCNT value matches that of the CMCOR, the CMCNT is cleared to H'0000 and the CMF flag
of the CMCSR is set to 1.
The CMCNT0 is initialized to H'0000 by resets. It retains its previous value in standby mode.
Compare Match Constant Register (CMCOR)
The compare match constant register (CMCOR) is a 16-bit register that sets the compare match
period with the CMCNT.
The CMCOR is initialized to H'FFFF by resets. It retains its previous value in standby mode.
9.5.3
Period Count Operation
When a clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the STR0 bit
of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the CMCOR, the CMCNT counter is cleared to H'0000
and the CMF flag of the CMCSR register is set to 1. The CMCNT counter begins counting up
again from H'0000.
Figure 9.27 shows the compare match counter operation.
Operation
CMCOR
CMCNT value
H'0000
Figure 9.27 Counter Operation
Section 9 Direct Memory Access Controller (DMAC)
Counter cleared by
CMCOR compare match
Rev. 5.00 May 29, 2006 page 295 of 698
Time
REJ09B0146-0500