HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 332

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 Direct Memory Access Controller (DMAC)
Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of
CHCR_0 to CHCR_3 (one byte, word, or longword, or 16-byte data).
Rev. 5.00 May 29, 2006 page 282 of 698
REJ09B0146-0500
Bus cycle
Bus cycle
Cycle-Steal Mode
In the cycle-steal mode, the bus right is given to another bus master after a one-transfer-unit
(8-, 16-, or 32-bit unit) DMA transfer. When another transfer request occurs, the bus rights are
obtained from the other bus master and a transfer is performed for one transfer unit. When that
transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer
end conditions are satisfied.
In the cycle-steal mode, transfer areas are not affected regardless of settings of the transfer
request source, transfer source, and transfer destination. Figure 9.14 shows an example of
DMA transfer timing in the cycle steal mode. Transfer conditions shown in the figure are:
Burst Mode
In the burst mode, once the bus right is obtained, the transfer is performed continuously
without passing it until the transfer end conditions are satisfied. In the external request mode
with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the
bus is passed to the other bus master after the DMAC transfer request that has already been
accepted ends, even if the transfer end conditions have not been satisfied.
The burst mode cannot be used when the serial communications interface (SCIF) and A/D
converter are the transfer request sources. Figure 9.15 shows a timing at this point.
DREQ
DREQ
Dual address mode
DREQ level detection
CPU
CPU
Figure 9.14 DMA Transfer Example in the Cycle-Steal Mode
Figure 9.15 DMA Transfer Example in the Burst Mode
CPU
CPU
CPU
CPU
DMAC
DMAC
Read
Read
DMAC
DMAC
Write
Write
Bus right returned to CPU
DMAC
Read
CPU
DMAC
DMAC
Read
Write
DMAC
DMAC
Write
Read
DMAC
CPU
Write
CPU
CPU