HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 37

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 1 Overview
Figure 1.1
Figure 1.2
Figure 1.3
Section 2 CPU
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Section 3 Memory Management Unit (MMU)
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3.8
Figure 3.9
Figure 3.10
Figure 3.11
Figure 3.12
Figure 3.13
Section 4 Exception Processing
Figure 4.1
Figure 4.2
Section 5 Cache
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
SH7706 Block Diagram.......................................................................................
Pin Assignment (FP-176C) ..................................................................................
Pin Assignment (TBP-208A) ...............................................................................
Register Configuration......................................................................................... 14
General Registers ................................................................................................. 15
System Registers.................................................................................................. 16
Control Registers ................................................................................................. 17
Data Format in Memory....................................................................................... 21
Processor State Transitions .................................................................................. 50
MMU Functions................................................................................................... 52
Virtual Address Space Mapping .......................................................................... 54
Overall Configuration of the TLB ....................................................................... 60
Virtual Address and TLB Structure ..................................................................... 61
TLB Indexing (IX = 1)......................................................................................... 62
TLB Indexing (IX = 0)......................................................................................... 63
Objects of Address Comparison .......................................................................... 64
Operation of LDTLB Instruction ......................................................................... 67
Synonym Problem................................................................................................ 69
MMU Exception Generation Flowchart............................................................... 74
MMU Exception Signals in Instruction Fetch ..................................................... 75
MMU Exception Signals in Data Access............................................................. 76
Specifying Address and Data for Memory-Mapped TLB Access........................ 78
Vector Addresses ................................................................................................. 82
Example of Acceptance Order of General Exceptions......................................... 84
Cache Structure.................................................................................................... 99
Cache Search Scheme (Normal Mode) ................................................................ 106
Write-Back Buffer Configuration ........................................................................ 107
Specifying Address and Data for Memory-Mapped Cache Access ..................... 110
Figures
Rev. 5.00 May 29, 2006 page xxxv of xlviii
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