HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 317
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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9.4.2
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by external devices and on-chip peripheral modules that are neither the
source nor the destination. Transfers can be requested in three modes: auto request, external
request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0
bits of CHCR_0 to CHCR_3.
Auto-Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits of CHCR_0 to CHCR_3 and the DME bit of
the DMAOR are set to 1, the transfer begins so long as the TE bits of CHCR_0 to CHCR_3 and
the AE but and NMIF bit of DMAOR are all 0.
External Request Mode: In this mode a transfer is performed at the request signal (DREQ) of an
external device. Choose one of the modes shown in table 9.2 according to the application system.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon a request at the DREQ input. Choose to detect DREQ by
either the falling edge or low level of the signal input with the DS bit of CHCR_0 to CHCR_1 (DS
= 0 is level detection, DS = 1 is edge detection). The source of the transfer request does not have
to be the data transfer source or destination.
Table 9.2
Note:
RS3
0
* External memory, memory-mapped external device, on-chip memory, on-chip
RS2
0
DMA Transfer Requests
peripheral module (excluding DMAC, UBC, and BSC)
Selecting External Request Modes with the RS Bits
RS1
0
1
RS0
0
0
1
Dual address
mode
Single address
mode
Address Mode
Section 9 Direct Memory Access Controller (DMAC)
Source
Any *
External memory,
memory-mapped
external device
External device with
DACK
Rev. 5.00 May 29, 2006 page 267 of 698
Destination
Any *
External device with
DACK
External memory,
memory-mapped
external device
REJ09B0146-0500
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