HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 496

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.1
The receive shift register 2 (SCRSR2) is an eight-bit register taht receives serial data. The CPU
cannot read from or write to the SCRSR2 directly. Data input at the RxD pin is loaded into the
SCRSR2 in the order received, LSB (bit 0) first, converting the data to parallel form. When one
byte has been received, it is automatically transferred to the SCFRDR2, which is a receive FIFO
register.
16.3.2
The 16-byte receive FIFO data register2(SCFRDR2) stores serial receive data. The SCIF
completes the reception of one byte of serial data by moving the received data from the SCRSR2
into the SCFRDR2 for storage. Continuous receive is possible until 16 bytes are stored.
The CPU can read but not write the SCFRDR2. When data is read without received data in the
SCFRFR2, the value is undefined. When the received data in this register becomes full, the
subsequent serial data is lost.
16.3.3
The transmit shift register 2 (SCTSR2) is an eight-bit register that transmits serial data. The CPU
cannot read from or write to the SCTSR2 directly. The SCI loads transmit data from the
SCFTDR2 into the SCTSR2, then transmits the data serially from the TxD pin, LSB (bit 0) first.
After transmitting one data byte, the SCI automatically loads the next transmit data from the
SCFTDR2 into the SCTSR2 and starts transmitting again.
16.3.4
The transmit FIFO data register 2 (SCFTDR2) is a 16-byte FIFO register that stores data for serial
transmission. When the SCIF detects that the SCTSR is empty, it moves transmit data written in
the SCFTDR2 into the SCTSR2 and starts serial transmission. Continuous serial transmission is
performed until the transmit data in the SCFTDR2 becomes empty. The CPU can always write to
the SCFTDR2.
When the transmit data in the SCFTDR2 is full (16 bytes), next data cannot be written. If
attempted to write, the data is ignored.
Rev. 5.00 May 29, 2006 page 446 of 698
REJ09B0146-0500
Receive Shift Register 2 (SCRSR2)
Receive FIFO Data Register 2 (SCFRDR2)
Transmit Shift Register 2 (SCTSR2)
Transmit FIFO Data Register 2 (SCFTDR2)