HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 321

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 9.4 shows how the priority order changes when channel 0 and channel 3 transfers are
requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The
DMAC operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
4. When the channel 0 transfer ends, channel 0 becomes lowest priority.
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
6. When the channel 1 transfer ends, channel 1 becomes lowest priority.
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel
transfer).
waiting)
(channel 3 waits for transfer).
3 becomes the lowest priority.
Transfer request
(1) Channels 0 and 3
(3) Channel 1
Figure 9.4 Changes in Channel Priority in Round-Robin Mode
Waiting channel(s)
1,3
3
3
None
(2) Channel 0 transfer
(4) Channel 0 transfer
(5) Channel 1 transfer
(6) Channel 1 transfer
(7) Channel 3 transfer
(8) Channel 3 transfer
start
ends
starts
ends
starts
ends
Section 9 Direct Memory Access Controller (DMAC)
DMAC operation
Rev. 5.00 May 29, 2006 page 271 of 698
Priority order
changes
Priority order
changes
Priority order
changes
Channel priority
0 > 1 > 2 > 3
1 > 2 > 3 > 0
2 > 3 > 0 > 1
0 > 1 > 2 > 3
REJ09B0146-0500